The disclosure relates generally to methods and apparatus for indicating status of integrated circuits, and more particularly, to methods and apparatus for indicating multi-power rail status of integrated circuits.
In an integrated circuit having multiple power rails and an input/output (I/O) transmitter, it is necessary to control the state of the I/O transmitter during the power-up and power-down conditions. This can be accomplished by using a status signal, also known as a “powergood” signal. When the status signal is logic high, it indicates that all power rails of the integrated circuit are fully powered up and the I/O transmitter can be controlled by core logic of the integrated circuit. When the status signal is logic low, one or more power rails in the integrated circuit are not fully powered up and the I/O transmitter can be put into a known state, such as a tri-state, a pull-up state or a pull-down state.
Particularly, the timing of the status signal is critical to the correct operation of the I/O transmitter. During power-up, if the status signal is asserted before the core logic of the integrated circuit becomes stable (i.e., all control signals from the core logic are valid), the I/O transmitter outputs an unpredictable state. On the other hand, during power-down, it is desirable for the status signal to be de-asserted immediately after the core logic becomes unstable (i.e., the control signals from the core logic are invalid).
One way to provide the status signal and regulate the timing of the status signal is to use an external off-chip power management module coupled to the integrated circuit to set a power sequence of all power rails during power-up and power-down, and to provide an external status signal (e.g., a powergood signal) to the I/O transmitter after all the power signals have ramped up. For example, for an integrated circuit having a first core logic power supply (VDDC), a second core logic power supply (VDDCI), and an I/O power supply (VDDR), the external off-chip power management module, during power-up, sets the core logic power supplies VDDC, VDDCI to be powered-up prior to the I/O power supply VDDR. While during power-down, the external off-chip power management module sets the I/O power supply VDDR to be powered-down prior to the core logic power supplies VDDC, VDDCI.
The external off-chip power management module, however, adds complexity to the integrated circuit design as each one of the power rails has to be controlled to follow the power sequence set by the external off-chip power management module. Moreover, as the external off-chip power management module provides the status signal only based on the state of the power rails, it does not consider the possibility that, during power-up, the core logic may not become stable even though all the power rails are powered-up. In this case, the external off-chip power management module still asserts the status signal to the I/O transmitter, and thus, causes the I/O transmitter to receive invalid data signals from the core logic before the core logic becomes stable.
Accordingly, there exists a need for improved methods and apparatus for indicating multi-power rail status of integrated circuits.